A prediction model for implementing DVS in single-rail bundled-data handshake-free asynchronous circuits

This paper explores the use of dynamic voltage scaling (DVS) for a particular type of asynchronous circuits, namely the single-rail bundled-data handshake-free asynchronous circuits. With respect to their synchronous counterparts, applying DVS to the targeted type of circuits imposes additional timing constraints that must be met to ensure correct operation. A new model defining these additional constraints is proposed. Such DVS related constraints were never explicitly formulated. The proposed model considers setup and hold timing constraints and transition degradation to ensure proper timing closure. Reported simulation results show that the timing constraints can be satisfied while applying DVS, but also that adjustments might be required to ensure proper pulse propagation and efficient operations.