Résumé
Power integrity issues and voltage fluctuations on power rails in emerging system-in-packages (SiP) that integrate switch-mode converters can impede the performances of embedded sensitive analog devices. Indeed, the progress of power device downsizing allows higher switching frequencies and shorter switching times, which create significant high-frequency switching noise in power rails. More specifically for converters that operate under a range of loading, gate driving and biasing conditions, a behavioral model is necessary in the context where simulation only is not sufficient for proper prediction of the power integrity characteristics of a system under that range of conditions. This article proposes a power integrity model and a characterization methodology to predict voltage fluctuations on the power rails in simultaneous switching conditions on an array of switch-mode converters integrated in SiP. Results show that for every condition studied in this work, accuracy better than 6 dB, aside from some limited discrete frequencies, is obtained between 0 and 1.9 GHz when the fluctuations caused by a single or multiple converters are measured. In terms of overall shape, for every condition studied both under simultaneous switching or not, the variance-normalized mean squared error is in a worst case of 0.624 and under numerous conditions better than 0.25.
| langue originale | Anglais |
|---|---|
| Pages (de - à) | 316-327 |
| Nombre de pages | 12 |
| journal | IEEE Transactions on Electromagnetic Compatibility |
| Volume | 67 |
| Numéro de publication | 1 |
| Les DOIs | |
| état | Publié - 2025 |
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