TY - GEN
T1 - Optimization of CRC-Based Single-Bit Error Correction Using a Perfect Hash Table Structure
AU - Ziani, Zouhair
AU - Coulombe, Stéphane
AU - Coudoux, François Xavier
AU - Corlay, Patrick
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - This work introduces a novel approach for correcting a single-bit error in a CRC-protected message, which is based on a perfect hash table that can be queried by a non-zero CRC syndrome. The paper primarily focuses on presenting the new table structure and includes a comparative analysis of various CRC-based error correction methods, demonstrating that ours strikes an excellent balance between correction complexity and memory requirements. Complexity evaluation is performed in terms of the number of 2-input gate operations.
AB - This work introduces a novel approach for correcting a single-bit error in a CRC-protected message, which is based on a perfect hash table that can be queried by a non-zero CRC syndrome. The paper primarily focuses on presenting the new table structure and includes a comparative analysis of various CRC-based error correction methods, demonstrating that ours strikes an excellent balance between correction complexity and memory requirements. Complexity evaluation is performed in terms of the number of 2-input gate operations.
KW - Cyclic redundancy check
KW - complexity
KW - hash table
KW - memory
KW - single-bit error correction
KW - syndrome computation
UR - https://www.scopus.com/pages/publications/105010576325
U2 - 10.1109/ISCAS56072.2025.11043197
DO - 10.1109/ISCAS56072.2025.11043197
M3 - Contribution to conference proceedings
AN - SCOPUS:105010576325
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Y2 - 25 May 2025 through 28 May 2025
ER -