Accelerating assertion assessment using GPUs

Jason G. Tong; Marc Boulé; Zeljko Zilic

doi:10.1109/HLDVT.2016.7748249

Accelerating assertion assessment using GPUs

Jason G. Tong
, Marc Boulé
, Zeljko Zilic

McGill University

Research output: Contribution to Book/Report types › Contribution to conference proceedings › peer-review

Abstract

In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.

Original language	English
Title of host publication	2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	9-16
Number of pages	8
ISBN (Electronic)	9781509042708
DOIs	https://doi.org/10.1109/HLDVT.2016.7748249
Publication status	Published - 17 Nov 2016
Event	18th IEEE International High Level Design Validation and Test Workshop, HLDVT 2016 - Santa Cruz, United States Duration: 7 Oct 2016 → 8 Oct 2016

Publication series

Name	2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016

Conference

Conference	18th IEEE International High Level Design Validation and Test Workshop, HLDVT 2016
Country/Territory	United States
City	Santa Cruz
Period	7/10/16 → 8/10/16

Access to Document

10.1109/HLDVT.2016.7748249

Cite this

Tong, J. G., Boulé, M., & Zilic, Z. (2016). Accelerating assertion assessment using GPUs. In 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016 (pp. 9-16). Article 7748249 (2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HLDVT.2016.7748249

@inproceedings{c77532082b5f49168ed0a07fbfecdea3,

title = "Accelerating assertion assessment using GPUs",

abstract = "In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.",

author = "Tong, \{Jason G.\} and Marc Boul{\'e} and Zeljko Zilic",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 18th IEEE International High Level Design Validation and Test Workshop, HLDVT 2016 ; Conference date: 07-10-2016 Through 08-10-2016",

year = "2016",

month = nov,

day = "17",

doi = "10.1109/HLDVT.2016.7748249",

language = "English",

series = "2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "9--16",

booktitle = "2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016",

}

Tong, JG, Boulé, M & Zilic, Z 2016, Accelerating assertion assessment using GPUs. in 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016., 7748249, 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016, Institute of Electrical and Electronics Engineers Inc., pp. 9-16, 18th IEEE International High Level Design Validation and Test Workshop, HLDVT 2016, Santa Cruz, United States, 7/10/16. https://doi.org/10.1109/HLDVT.2016.7748249

Accelerating assertion assessment using GPUs. / Tong, Jason G.; Boulé, Marc; Zilic, Zeljko.
2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 9-16 7748249 (2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016).

Research output: Contribution to Book/Report types › Contribution to conference proceedings › peer-review

TY - GEN

T1 - Accelerating assertion assessment using GPUs

AU - Tong, Jason G.

AU - Boulé, Marc

AU - Zilic, Zeljko

PY - 2016/11/17

Y1 - 2016/11/17

N2 - In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.

AB - In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.

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DO - 10.1109/HLDVT.2016.7748249

M3 - Contribution to conference proceedings

AN - SCOPUS:85006371499

T3 - 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016

SP - 9

EP - 16

BT - 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th IEEE International High Level Design Validation and Test Workshop, HLDVT 2016

Y2 - 7 October 2016 through 8 October 2016

ER -

Accelerating assertion assessment using GPUs

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