Efficient FPGA Acceleration of Deep Neural Networks for Image Processing Using an OpenCL-Based High-Level Synthesis Framework

Deep Neural Networks (DNNs) have become central to modern signal and image processing systems. However, their high computational complexity imposes significant challenges for hardware implementation, particularly in terms of resource utilization, latency, and energy efficiency. Field-Programmable Gate Arrays (FPGAs) provide a promising platform for accelerating DNN workloads, offering parallelism and reconfigurability. Nevertheless, conventional HDL-based designs lack portability, while existing OpenCL flows often rely on heuristic exploration, leading to unpredictable performance and inefficient hardware utilization. To address these challenges, this paper proposes a metrics-driven predictive methodology for FPGA-based DNN acceleration using an OpenCL-based high-level synthesis framework. The proposed framework integrates profiling-driven kernel selection, computational intensity analysis, predictive performance modelling, and HLS optimizations into a closed-loop design flow. Quantitative models for speedup, throughput, loop latency, overlap efficiency, and BRAM feasibility are introduced to systematically guide architectural and optimization decisions prior to hardware deployment. The framework was validated on a Xilinx Zynq-7000 FPGA using MNIST and CIFAR-10 image classification benchmarks, two common image classification benchmarks. Experimental results achieved 97.81% recognition accuracies on MNIST and 82% on CIFAR-10, while maintaining a low power envelope of 1.98–2.14 W. The proposed framework delivered speedups of up to 8.37× and 9× compared to CPU-only baseline execution. Beyond these results, this work validates how predictive modeling can help guide FPGA design choices in a way that improves both efficiency and portability for signal and image-processing-oriented DNN acceleration.