Functional constraint extraction from register transfer level for ATPG

Keyphrases

• Automated Tool 33%
• Constraint Extraction 100%
• Coverage Time 33%
• Design Simulation 33%
• Error Detection 66%
• False Error 66%
• Functional Constraints 100%
• Gate-level 33%
• Generation Process 33%
• Generation Tools 33%
• Hardware Description Language 33%
• Reachable States 66%
• Register Transfer Level 100%
• Scan Test 66%
• Test Generation 100%
• Test Pattern 66%
• Unwanted Behaviors 33%
• Verification Environment 33%
• Verification Process 33%

Computer Science

• Automated Tool 50%
• Design Simulation 50%
• Error Detection 100%
• Experimental Result 50%
• Hardware Description Languages 50%
• Register-Transfer Level 100%
• Verification Environment 50%
• Verification Process 50%