Impulse Radio Ultra Wide Band (IR-UWB) has recently received significant attention for short-range wireless communication applications. The unique properties of IR-UWB systems have made them more prevalent in today’s wearable and Internet of Things (IoT), sensor nodes, healthcare devices and smartphones.
A variety of transceiver architectures in the IR-UWB system have been proposed by researchers over the past decade, including coherent and non-coherent architectures, which can improve one or more challenges associated with the IR-UWB systems. This thesis aims to realize a low-power efficient coherent IR-UWB system. In order to reduce the energy consumption of conventional coherent receivers, a hybrid synchronization algorithm for the coherent receivers is proposed. Prior to a coherent synchronization, the algorithm uses a non-coherent assisted synchronization to limit the search space. Compared to conventional coherent receivers, this method greatly reduces the amount of power used for receiver synchronization.
The proposed hybrid synchronization method begins with a non-coherent synchronization mechanism based on energy detection using On-Off Keying (OOK) modulation to coarsely synchronize the receiver by determining the correct integration window in which the received signal resides. Once the coarse synchronization level is achieved, a coherent template-based coherent correlation employing Binary Phase-Shift Keying (BPSK) modulation is carried-out for fine synchronization and to benefit from coherent payload decoding.
A prototype IR-UWB receiver operating from 3.5 to 5 GHz has been implemented in a TSMC 65 nm CMOS technology. Our proposed receiver architecture enabled us to compare our hybrid synchronization approach to two common receiver architectures, namely non-coherent energy detection and coherent detection receivers.
The receiver architecture utilizes a self-mixer for a non-coherent detection based on OOK modulation and a template correlation for a coherent detection based on BPSK modulation. Most blocks in the proposed receiver architecture, including the LNA, mixer and baseband circuitry are shared between the non-coherent and coherent modes to minimize the total power consumption and receiver area. A two-step coarse and fine acquisition mechanism is utilized to simplify the coherent synchronization and minimize the total required packet length. A multi-resolution Delay-Locked Loop (DLL) and a fast start-up Voltage Controlled Oscillator (VCO) provide the proper phase for the integration window and template generation.
The receiver consumes 6.8 mW in non-coherent mode and 8.8 mW in coherent mode when operating fully ON, excluding the power consumption of the buffers and the digital baseband processor. It achieves a -68 dBm, -70.5 dBm, and -70.8 dBm RF sensitivity at a 10−3 BER in the non-coherent, coherent, and proposed hybrid mode, respectively. Our proposed receiver architecture, in combination with the hybrid coherent synchronization algorithm, demonstrates that the proposed synchronization approach is capable of significantly reducing the overhead incurred by the preamble. The packet duration is reduced from 37.12 us dans le cas de corrélation cohérente à 24,42 us avec la méthode de synchronisation hybride proposée pour une charge utile de 1024 bits.
| Date | 22 Dec 2022 |
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| Original language | American English |
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| Awarding Institution | - École de technologie supérieure
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| Supervisor | Frédéric Nabki (Supervisor) |
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Pourvali Kakhki, A. (Author),
Nabki (Supervisor),
22 Dec 2022Student thesis: Master's thesis › Master in Engineering: Electrical Engineering