Adaptation de l'approche de test CDIDDQ aux circuits programmables FPGA

Abstract

This thesis proposes the adaptation of the CDIDDQ test technique, primarily developed for ASICs, to test configurable SRAM-Based FPGA circuits. After presenting the architecture of these target circuits and reviewing some of the test configuration literature, a general strategy for adapting the technique to test the interconnections of these circuits is proposed. The adaptation process starts with the experimental validation of the test technique by applying it to an ASIC circuit emulated in an FPGA. This results allows the use of this kind of technique for the application dependant testing and benefits of its coverage which can reach more than 90%. Secondly, the process is applied independently of the application. In this context, the adaptation of the technique is specifically done for testing some FPGA interconnects. For that purpose, a new configuration strategy is proposed to put all the interconnections in the shape of an interleaved comb structure. The proposed configuration is innovative and contributes to reduce test time. The strategy uses a new script-based auto- configuration tool, developed for the target FPGA interconnect, namely the horizontal north double lines in the Xilinx Spartan 3e FPGA. A very low cost test platform merging two commercial boards is designed to experimentally validate the concept. The results obtained show that 100% fault coverage is achieved with a significant reduction in test time compared to the existing solutions.

Date	24 Nov 2011
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)