Amélioration du processus de testabilité des circuits intégrés asynchrones dérivés de la topologie de conception d'Octasic

Abstract

Asynchronous circuits include a wide variety of design techniques. Octasic, a Montreal - based company, designs digital signal processors (DSPs) that are using a particular asynchronous technique of its own invention. This type of circuit has already been the subject of previous research that led to the development of an initial test method and analysis algorithm. Yet, automation of a method is often needed to be democratized, and this technique has never been dealt with. Hence, this thesis proposes to improve and automate as much as possible the previously-developed test method for asynchronous circuits that are using Octasic’s DSP structure. Unlike the initial method, the developed process supports testability of finite state machines and the management of complex clock networks that can contain registers. Across a variety of asynchronous circuits with variable complexity, we introduce a mostly-automated testability flow that starts from the synthesis of the design and runs until the test-vector simulation. In addition, it presents a program that can analyze internal structural arrangement of circuits to insert and connect specific modules of the test method. Finally, we explain how to write test procedures that are necessary to generate the test vectors with the automatic test-pattern generator (ATPG). We generate test vectors and simulate them to measure the efficiency of our test method. The tests conducted with the ATPG tool and the simulation of the tests vectors allow us to obtain a test coverage rate of 76.08%. These tests exploit the launch-on-capture technique at nominal speed on our most complex circuit, an asynchronous mini-MIPS microprocessor derived from Octasic’s DSP architecture and implemented with the 45nm Cadence technology.

Date	12 Sept 2019
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)