Amplificateur et détecteur d’enveloppe large-bande pour la polarisation dynamique des amplificateurs RF CMOS en rétroaction positive d’enveloppe

Abstract

5th generation (5G) technology for mobile communications aims to dramatically increase the number of devices on the network in addition to increasing bandwidth to offer more speeds to users. Although these changes are beneficial for mobile applications, IoT devices, autonomous cars, etc., they add pressure on the hardware system in place, particularly in terms of performance including energy consumption. The radiofrequency power amplifier is often the most energy-intensive element in mobile systems, and its presence is essential for wireless systems. Several techniques developed in the literature have demonstrated improved efficacy. In particular, the EER and ET approaches improve the trade-off of efficiency and linearity. Numerical approaches of predistortions also allow the improvement of this trade-off. Although they offer excellent performance, these approaches are complex, require a significant on-chip surface, and it could be difficult to integrate certain configurations in CMOS technology on a single chip. Based on a technology developed at ETS and patented by Skyworks Solutions Inc. in 2019, the PEF (Positive Envelope Feedback) technique has already demonstrated interesting potential as a solution for single-chip integration, for improving the efficiency and linearity trade-off of RF power amplifiers. The technique uses positive envelope feedback to dynamically adjust the gate bias of the power amplifier. Also, this approach benefits from a large bandwidth which proves attractive for modern communication systems while having a small on-chip footprint. A new type of radio frequency envelope detector has been developed with 180 nm CMOS technology for a frequency of 5.4 GHz in order to meet the specific criteria of the PEF technique. Characterization of the chip in simulation demonstrated an envelope bandwidth of 842 MHz with a static power consumption of 7.5 mW with a supply voltage of 1.8 V. The small on-chip footprint, simplicity, and good carrier rejection make this structure interesting and competitive compared to other topologies in the literature. A differential radiofrequency amplifier with two stages « stacked-FET » structure operating at 5 GHz has been designed with 180 nm CMOS technology. Experimental results demonstrated a gain of 12.6 dB with a compression point of 10.37 dBm. The 3 dB bandwidth was measured at 480 MHz. Finally, two envelope detectors developed in this work were added to the output of the amplifier in order to validate the broadband performance of the PEF technique. Also, the great simplicity of integration in comparison with other techniques for improving the efficiency and linearity trade-off found in the literature has been demonstrated. In this configuration, the newly developed envelope detector uses less than 3.5% of the on-chip area and a power consumption of less than 5% compared to that of the radio frequency amplifier.

Date	7 Jun 2023
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Nicolas Constantin (Supervisor)