Caractérisation et analyse des chemins critiques de circuits intégrés asynchrones complexes

Abstract

This thesis addresses the verification and design of complex asynchronous circuits. Complex implies the design on non-trivial circuits, like microprocessors. Circuits and designs made today contain more and more functions. Hence, they contain a growing number of transistors. The designs can implement increasingly complex functions compared to older circuits, but they also need more energy to execute them. Mobile phones and devices also need to be more and more powerful. However their battery-based power supplies cannot efficiently feed a power-hungry processor. A method that can be used to create powerful yet energy efficient devices is the asynchronous methodology. The asynchronous paradigm is interesting because it doesn’t require a global clock signal. It is replaced by inter-module synchronization methods. This eliminates the need for a global clock distribution network while reducing the number of useless transitions in the device. Without a global clock network and useless transitions, the device can have a lower power consumption. Since the traditional way to create digital circuits is based on the synchronous paradigm, asynchronous oriented CAD tools are mostly unavailable. Indeed, the synchronous methodology is integrated and automated by CAD tools. These tools allow the designer to synthesize the design and to assure the timing closure of the design. There are also tools that enable the designer to create test patterns used to test the chip once it’s created in silicon. To further the acceptance of the asynchronous paradigm, there must be tools that adapt the usage of traditional tools. This entails that the tools are adapted to the paradigm without necessarily adapting the designers to the paradigm. The tool developed in this thesis, named qmi, succesfully generalizes the concept of timing analysis by allowing the presence of combinational logic in the clock paths. Theses structures are bounded by configurations that were discovered by the analysis of circuits produced by the methodology used by the Octasic company. Moreover, the tool generates configuration files to be used with Tessent by Mentor Graphics. Tessent is a tool suite used to adapt circuits for testing and to create test patterns. Thus, qmi can adapt traditional tools to the asynchronous paradigm thereby solving the initial problem caused by the lack of tools.

Date	30 Oct 2014
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor) & François Gagnon (Co-supervisor)