Mulilevel topologies attract more interest in the field of medium and high power converters as a result of their scalability and flexibility. This trend is supported by academic and industrial research which tackle the known issues and limitations of this new technology. Defining reliable numerical models is one objective of this work since it is the starting point to develop new control algorithm.
The goal of this master thesis is to design a Modular Multilevel Converter (MMC) test bench to perform experimental validation of numerical models. This project is made within a partnership with Opal-RT which specializes in the field of real-time simulation. The proposal is to build a lab-scale MMC test bench which directly connects to an Opal-RT simulator. To achieve this, a serial communication link with a 550 ns latency is developed to transmit control signals to a local submodule controller. The design process of this link and the development of the submodules is decribed in details. The components tests are shown progressively during the design process.
This works ends with the assembly of a complete 60 submodules prototype to operate as a 11 levels DC-AC three phase converter. A submodule voltage balancing algorithm based on sorting is implemented on FPGA. The experimental results of this control are given for a 4.65 kW operating point.
| Date | 15 Jun 2016 |
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| Original language | French |
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| Awarding Institution | - École de technologie supérieure
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| Supervisor | Handy Fortin Blanchette (Supervisor) |
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Rivest, J. (Author),
Fortin Blanchette (Supervisor),
15 Jun 2016Student thesis: Master's thesis › Master in Engineering: Electrical Engineering