Conception et réalisation CMOS d'un détecteur de puissance RF pour un système automatique d'apadptation d'impédance

Abstract

An RF power detector is a critical component of AIMS (Automatic Impedance Matching Systems) which are increasingly used in wireless communication devices. The RF power detector characteristics have a significant importance on AIMS performances. First, the impedance matching accuracy of the AIMS is linked to the dynamic range of the power detector. Also, the insertion loss of the AIMS is determined by the sensitivity of the power detector. Furthermore, the power consumption of the power detector is typically a significant proportion of the AIMS overall power consumption. Therefore, the main advantage of using an AIMS - the increase of the wireless communication system efficiency - is directly linked to the performances of its RF power detector. The subject of this Thesis is the design and implementation of a novel RF power detector architecture for an AIMS to be integrated in a System on a Chip. The dynamic range of the power detector is distributed over three low power consumption detection units. This architecture allows operating the transistors in their optimum polarization region over a wider dynamic range than other recently published low-power CMOS RF power detectors. Hence, the dynamic range of the proposed RF power detector is comparable to the dynamic range obtained by limiting-amplifier power detectors, which are typically employed in CMOS power detection, but with lower power consumption. This document presents the design of the distributed RF power detector and its CMOS implementation. An integrated circuit was fabricated using a CMOS 0.13 μm process provided by IBM through CMC Microsystems. The chip area is 2 mm2 (including bonding pads). Experimental results show a 35 dB dynamic range over a frequency range from 500 MHz to 4 GHz. The power consumption of the integrated circuit is 0.554mW. These results outperform those of recently published work in this field. The RF power detector designed during this Master’s degree will be the topic of a publication at the IEEE NortheastWorkshop on Circuit and Systems (IEEE NEWCAS 2011).

Date	6 May 2011
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Ghyslain Gagnon (Supervisor) & Ammar B. Kouki (Co-supervisor)