Développement d'une infrastructure pour l'accélération sur matériel de la simulation numérique

Abstract

In microelectronics, the verification of digital systems is a step in the design that is becoming increasingly important in terms of time and resources invested. This check is crucial because it helps to demonstrate the proper functioning of the system at the behavioural and physical level prior to its implementation. It is possible to facilitate and improve the overall verification process using an innovative approach of comparative evaluation using the "Hardware In the Loop" (HIL). This technique can replace the calculations of numerical simulation software based on calculations derived from physical hardware that works in reality. The HIL comparative verification approach that we are proposing uses a friendly infrastructure that allows digital processing to simulate on a hardware platform near the platform used after conception by using stimuli from MATLAB. This approach allows the early detection of insurmountable obstacles, which contributes to a global acceleration of the verification process for digital systems. The development of this infrastructure has led to the creation of an FPGA development project supporting the HIL, the creation of a DUV encapsulation core, the development of data management software and the development of GUI software for HIL control. Analysis of the results of HIL was reached using three scenarios. The cases have showed that it is possible to facilitate and accelerate the overall verification process using a verification approach that uses HIL simulation.

Date	9 Sept 2010
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)