FPGA-based solutions for secure cryptocurrency wallets and accelerated smart contract execution

Abstract

Blockchain technology enables tamper-resistant and transparent data management, but it continues to face pressing challenges related to security and performance. Existing blockchain applications predominantly rely on software-based implementations, which are susceptible to side-channel analysis (SCA) attacks and constrained by the limited efficiency of general-purpose processors. This thesis addresses these challenges by leveraging Field-Programmable Gate Array (FPGA) technology to develop hardware-based solutions that strengthen cryptographic security and accelerate blockchain execution. Three major hardware contributions are presented: an Ethereum hardware wallet resistant to SCA, a hybrid Ethereum–Bitcoin hardware wallet supporting both Hierarchical Deterministic (HD) and Non-Deterministic (ND) modes, and a hardware-accelerated Ethereum Virtual Machine (EVM). The first contribution, EthVault, introduces the first complete hardware architecture of an Ethereum HD cold wallet and its FPGA implementation. EthVault integrates a side-channel resistant elliptic curve cryptography (ECC) design, the first hardware realization of the child key derivation (CKD) function, and resource-conscious implementations of key cryptographic algorithms, including ECDSA, HMAC-SHA-512, PBKDF2, SECP256K1, elliptic curve point operations, and the Ethereum checksum algorithm, resulting in a secure, compact wallet. The second contribution, HardVault, presents the first FPGA-based hybrid Ethereum–Bitcoin cold wallet architecture. Supporting both HD and ND key generation methods, HardVault improves resource efficiency by reusing cryptographic primitives common to Ethereum and Bitcoin, including RIPEMD-160, CKD, and SHA-256. This reuse minimizes hardware overhead, enabling a lightweight and energy-efficient solution. A detailed power–performance evaluation further demonstrates HardVault’s superior efficiency, with measurable improvements over commercial wallets such as Trezor One. The third contribution, EVMx, proposes a single-core FPGA-based EVM that offloads smart contract execution from full and archival nodes to a dedicated hardware accelerator. EVMx preserves full compatibility with the EVM’s stack-based semantics while introducing performance optimizations such as lightweight pipelining, simplified opcode decoding, dynamic corner-case handling, and selective parallelism. Experimental results show significant speedups for both individual opcodes and complete smart contract execution compared to CPU-based and prior FPGA designs. Furthermore, integration strategies are discussed to enable scalable adoption of EVMx within existing Ethereum clients. Overall, this thesis demonstrates that FPGA-based designs can substantially strengthen blockchain ecosystems by enhancing both security (EthVault and HardVault) and computational performance (EVMx), thereby paving the way for more secure, efficient, and practical blockchain deployments.

Date	23 Dec 2025
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Pascal Giard (Supervisor) & Kaiwen Zhang (Co-supervisor)