This thesis investigates the design, control, and implementation of grid-tied AC-DC conversion systems that prioritize high power density, long lifetime, and compatibility with cost-sensitive digital controllers. The work focuses on single-phase power factor correction (PFC) front ends for electric vehicle on-board chargers, data center and telecom rectifiers, and similar single-phase interfaces, and extends the underlying design principles to a representative three-phase isolated PFC rectifier. Across these applications, the main bottlenecks for further gains in density and reliability are the magnetic and capacitive passive components required for energy buffering, electromagnetic interference (EMI) filtering, and output decoupling. The central purpose is to reduce passive-component volume while meeting stringent power-quality, efficiency, and lifetime targets, using flying-capacitor multilevel (FCML) topologies combined with advanced, microcontroller optimized model predictive control (MPC) schemes.
The thesis first develops a compact comparison framework for single-phase PFC front ends that covers bridgeless totem-pole stages, FCML totem-pole variants with different level counts and interleaving factors, and related multilevel and hybrid structures. Under consistent few-kilowatt specifications and continuous-conduction operation, analytic sizing laws are introduced for boost inductors, flying-capacitor stacks, and EMI filters. These laws are combined with equal-loss constraints and simple volume metrics derived from energy density, yielding structural tables that map topology and control choices to passive volume and qualitative EMI implications. This framework provides a systematic basis for selecting promising single-phase FCML candidates as density levers.
On the hardware and control side, a 2.5 kW single-phase totem-pole five-level FCML PFC prototype is designed and implemented with a three-board partition (power stage, sensor and interface board, and digital controller). Linear control with phase-shifted PWM, current and voltage loops with feedforward, and active flying-capacitor balancing are realized on a C2000 microcontroller platform and validated experimentally with high efficiency, near-unity power factor, and controlled DC-link ripple. Building on this platform, the thesis develops and experimentally validates finite-control-set MPC schemes for a four-level FCML OBC front end that support unified grid-following and grid-forming operation across multiple vehicle-to-everything modes, and for a four-cell flying-capacitor PFC converter with integrated power pulsation buffering that embeds twice-line-frequency energy storage into the FC stack. A two-stage lexicographic, weight-free MPC structure is then introduced to eliminate weighting-factor tuning and guarantee deterministic execution within a 6.66 microsecond sampling period on a dual-core microcontroller, while achieving substantial DC-link ripple reduction and passive-volume savings.
Finally, a three-phase isolated matrix-type PFC rectifier with duty-cycle loss compensation and reactive power support is analyzed as an example of a high-density front end that removes the intermediate DC-link capacitor and integrates isolation and PFC in a single stage. The combined results demonstrate that FCML PFC topologies with integrated buffering, supported by carefully structured MPC implementations on commercial microcontrollers, offer a practical path to compact, efficient, and reliable AC-DC interfaces. The thesis recommends the use of the proposed comparison framework and control architectures as design tools for next-generation single-phase and three-phase front ends in EV charging, data centers, and telecom power supplies.
| Date | 20 Dec 2025 |
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| Original language | American English |
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| Awarding Institution | - École de technologie supérieure
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| Supervisor | Ambrish Chandra (Supervisor) |
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Patel, P. (Author),
Chandra (Supervisor),
20 Dec 2025Student thesis: Doctoral thesis › Doctorate in Engineering: Engineering