Méthodes d’instrumentation et d’optimisation d’applications élaborées en OpenCL mise en oeuvre sur des plateformes hétérogènes reconfigurables

Abstract

The need for high-performance computing platforms has recently intensified with the emergence of new applications, such as artificial intelligence and data science. New reconfigurable heterogeneous platforms are thus deployed with a much greater potential of computational acceleration than those based on a multiprocessor architecture. These platforms are powered with several computing elements such as multi-core processing units (CPUs), specialized processors for graphic processing (GPUs) and field-programmable gate arrays (FPGAs). FPGA vendors now offers high-level synthesis (HLS) tools to support this architectural diversity. On the other hand, the performance of an application created by these HLS tools is strongly dependent on its high-level description, which is generally less competitive with that described with low-level hardware description languages. Moreover, this performance degradation is difficult to analyze and diagnose, since these HLS tools do not provide a mechanism to analyze the causes of this degradation like those that exist for CPUs and GPUs. The main objective of the work presented in this thesis is to improve the productivity of application development on FPGA-based reconfigurable heterogeneous platforms. This work aims to improve the observation of temporal events, in FPGA-based accelerators described in OpenCL, paving the way for the precise diagnosis of performance losses such as pipeline stalls. Another specific objective is to ease the elaboration of optimization methodologies to improve the performance of FPGA-based accelerators described in OpenCL. The first contribution of this thesis proposes a solution for the in-situ analysis of timing performance of an OpenCL kernel implemented in FPGA by integrating a monitor developed with a hardware language. This monitor can easily be integrated into OpenCL kernels through hardware/software design approach. It can then extract runtime information at FPGA clock cycle accuracy. The second contribution exploits this new instrumentation method by proposing a framework to extract the timing performance of OpenCL kernels. A theoretical model is proposed to identify the number of instruments to be inserted to precisely compute the timing performance of an application. To the best of our knowledge, the proposed instrumentation framework is the first framework that proposes the measurement of timing performance such as latency and initiation intervals of loops and to identify performance bottlenecks of OpenCL-based designs on FPGA. The third and fourth contributions of this thesis open the door to design an automatic optimization tool and methodology for OpenCL-based designs on FPGA. Indeed, OpenCLbased optimization techniques are proposed to accelerate OpenCL-based designs and they are applied to the secure hash algorithms (SHA) SHA-2 and SHA-3. The results showed that implementations of SHA-2 and SHA-3 derived from OpenCL descriptions offer throughputs of 3.9 Gbps and 22.36 Gbps respectively, which are 4.3 times and 2 times higher than the best previously published HLS-based designs.

Date	15 Oct 2021
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Yves Blaquière (Supervisor) & Yvon Savaria (Co-supervisor)