Over the last few decades, technology scaling has continuously brought new challenges to the research community, from integrated circuit (IC) design to IC testing. Industry estimates that functional verification takes approximately 50% to 70% of the total effort on a project. And even with verification budgets dominating design budgets, there are increasingly more bug escapes through fabrication and consequently expensive re-spins. Verification methodologies are grouped into two main categories: 1) Simulation-based methods and 2) formal methods.
Although both methodologies are now widely established for design verification, simulationbased verification remains the most commonly used technique. Yet, simulation has clearly failed to keep pace with complexity and faces lots of challenges. Therefore, with the continuous competition growth in products and services along with the harsh law of time to market, innovative solutions are required. Hence, a transition to new methodologies and tools is deemed crucial.
Several techniques have been developed to overcome simulation-based verification challenges, ranging from fully manual to advanced testbenches. The manual and semi-manual techniques cannot be scaled on complex designs, and the more advanced approaches that are commonly used in the industry, need special skills and human interaction to achieve good verification productivity.
From a test perspective, the use of structural approaches based on fault models and on design for testability (DFT) concepts (namely scan-based), has led to the development of efficient automatic test pattern generation (ATPG) tools. The resulting test infrastructure has greatly helped the test community to address previous encountered issues and to face the incoming ones.
In this thesis, we are primarily concerned with the productivity of the verification process, more specifically the verification of sequential circuits. We propose a new methodology that explores a new test/verification combination, namely the use of structural test patterns in the RT simulation-based verification process. This methodology is aimed to reduce time and effort required to verify a circuit and to improve the resulting coverage, inducing significant improvements in verification quality and productivity. The cornerstone of the proposed methodology is the intuition (that became an observation) according to which a node that is difficult to test (Hard Fault) is likely difficult to verify (Dark Corner).
The goal is to take advantage of the efficient test tools as ATPG, and the advanced test techniques as scan-based DFT to simulate and exercise efficiently the model functionality with minimum time and effort. Based on all these concepts, we introduced an automated RTL verification environment composed of three basic tools: 1) A constraint extractor that identifies design’s functional constraints, 2) a test bench generator tool, and 3) an error tracker based on a high observability.
Experimental results showed the effectiveness of the proposed verification methodology. It could fast provide fault and code coverage that are equal to and even higher than one obtained with other well known simulation-based verification approaches. In addition to the coverage improvements, there is a remarkable reduction in effort and time needed to verify the designs. Unlike the other methodologies, the proposed approach requires little effort, in order to accomplish the simulation.
Hobeika, C. (Author),
Thibeault (Supervisor) &
Boland (Co-supervisor),
4 Oct 2011Student thesis: Doctoral thesis › Doctorate in Engineering: Engineering