Méthodologie parallèle hybride appliquée au décodage H.264/MPEG-4 AVC supportant la résolution HD sur un processeur DSP asynchrone multicoeurs

Abstract

In the field of mobile telephony, the adoption rate of the videoconferencing application is currently growing at a fast pace. In order for mobile phone providers to make a unified and standardized videoconferencing application available to a wider mass market, they must turn to more efficient, flexible, affordable and less power consuming solutions. New media gateways are now taking advantage of more powerful DSP-based multicore architectures. To take advantage of these DSP processors, the implementations of algorithms executed on these processors require to be distributed across multiple cores. One of these algorithms is the decoder from the H.264/MPEG-4 AVC specification. In this master’s thesis, we propose a new solution to parallel decoding applied to the H.264 baseline profile specification. This new solution takes advantage of the OCT1010 asynchronous multicore DSP processor architecture. This solution differs from those found in the literature mainly because it is the first parallel hybrid methodology applied to video decoding using a multicore DSP processor. The new solution proposed in this master‘s thesis uses several concepts of extensibility, especially through a resolution abstraction mechanism and on a generic and scalable intercommunication and synchronization mechanism that is based on the number of cores available on a DSP processor. In addition, we propose a new algorithm that improves the execution time of the fourth stage of the CAVLC entropy decoding algorithm which extracts of the total number of zeros inside a 4x4 block. Our implementation of the H.264/MPEG-4 AVC decoder, based on this solution, was tested using 7 video sequences encoded with different resolutions using different encoding bitrates. Our simulation results demonstrate that our new solution to parallel decoding applied to the H.264/MPEG-4 AVC decoder on an OCT1010 DSP processor meets real time constraints needed in the field of mobile applications for videoconferencing. Indeed, the solution proposed in this master‘s thesis applied to 11 DSP cores for the 720p HD resolution has a running time representing 130% of real time constraints compared to 18% for a sequential implementation using only one single DSP core. This represents a mean decoding time acceleration gain of 7.3.

Date	9 Aug 2012
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Stéphane Coulombe (Supervisor)