Méthodologies in situ d’identification de corruptions silencieuses de données dans un processeur RISC-V à l’aide de circuits FPGA

Abstract

In recent years, multiple large-scale server operators have reported a growing number of silent data corruptions in their processors. Silent data corruption is a type of processor failure in which corrupted data is generated without being immediately detected. The corrupted data can then spread undetected throughout the program and will generally only be noticed when it causes a problem, such as data loss. The silent nature of these faults complicates the isolation process. The main objective of the presented work was to develop and test in situ methodologies to identify silent data corruption in a processor. The sub-objectives were as follows : (1) develop a fault identification methodology based on a pre-existing program, (2) develop a fault identification methodology based on test program generation, and (3) develop a fault emulation methodology to test the aforementioned fault identification methodologies. Two fault identification methodologies have actually been developed. The first methodology compares the faulty execution of a pre-existing program with the simulated execution of the program to identify the source of the fault. The second methodology compares the frequency of fault manifestation in test programs with the frequency of use of certain processor resources to identify which processor resources are associated with the fault. This methodology uses generated programs. Additionally, a fault emulation methodology based on the use of fault injectors inside a RISC-V processor implemented in an FPGA has been developed. The emulation methodology has been used to validate the two fault isolation methodologies. Indeed, the emulation methodology has been used to inject faults on specific logic and arithmetic resources in the RISC-V processor, in addition to the input of the register file. The test results show that both methodologies can be used to isolate the fault source. The fault isolation methodology based on the frequency of fault manifestation is fully automated and was able to isolate 100% of all faults injected. This methodology is, however, limited in the number of faults it can detect. It is the main methodology developed. The results for the simulation-based methodology show that a certain level of manual analysis is required. In the future, the frequency-based testing methodology could be improved to support the detection of more complex faults. Additionally, both fault identification methodologies could be tested with different fault models, such as temporal faults.

Date	12 Aug 2026
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor) & Pascal Giard (Co-supervisor)