Millimeter-wave antenna selection switch using advanced CMOS technologies

Abstract

The main objective of this research work is to develop an innovative on-chip CMOS-based antenna switching circuit for fifth-generation (5G) mobile communication equipment. The specific objectives are to study, design, simulate, test, and validate the operation of the proposed CMOS-based antenna switching circuit operating at 28GHz. The switching circuit comprises an SPDT (Single Pole Double Throw) switch circuit on a single chip in CMOS technology, along with the necessary transmission lines embedded into a multi-layer laminate for the connection between the on-chip switch circuitry and the two antennas. The necessity for the coexistence of RF & mm-wave technologies (e.g., WLAN transceivers in 5GHz band and machine-to-machine communication transceivers in the 28GHz band) in future wireless communication equipment imposes integration design challenges in the Power Amplifier (PA) module intended for the transmitter front ends. A key aspect is the necessity to include mm-wave antenna switching capabilities in the same PA module while favoring miniaturization. This requires innovation in the design and integration of low-loss CMOS switching circuits on the same 28 GHz PA IC. It also complicates the design of the transmitter front-end, as it requires low-loss transmission paths from the Power Amplifier IC to different RF & millimeter-wave antenna locations on the communication equipment’s PCB. The starting point is the study of the design documentation on a basic structure of a millimeterwave antenna switch designed at Skyworks Solutions, Inc. An in-depth investigation accompanies this study through simulation of state-of-the-art switch architectures and circuit techniques proposed in the literature as well as other compatible industrial designs. This study is followed by the characterization of CMOS devices in conjunction with the design of switch circuitry. In particular, key switch performance metrics such as achieving lower insertion losses and good isolation with advanced CMOS technology is pursued and demonstrated through the design of an asymmetric SPDT fabricated using a 45nm CMOS SOI process. The measured insertion loss and isolation at 28GHz from Tx-to-Rx are 0.9dB and 28dB, respectively.

Date	16 Jul 2020
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Nicolas Constantin (Supervisor)