Optimized multilevel inverters and modulation techniques for power electronics applications

Abstract

The main goal of this thesis is to optimize the modulation techniques and multilevel inverter topologies to reach a higher efficiency in power electronics applications. Among conventional multilevel inverters, compact topologies like Packed U-Cell is interesting particularly for single phase applications because of single dc source structure. Five-level Packed U-Cell appeared as a promising topology that could find its way to industry; but, it confronts some drawbacks when it is extended to generate more levels. The main drawback is the capacitor voltage balancing issue which demands a deep optimization to reach a novel and reliable compact multilevel inverter topology. Along with optimization of the inverter topology, modulation techniques need to be optimized to enhance the inverters efficiency in the targeted applications. Although popular techniques like SVM and SPWM could show their reliable performance, they have high switching frequency which increases power losses. On the other hand, SHE-PWM and SHM-PWM were introduced as a promising low switching frequency techniques where, they can be the appropriate candidates for optimization and utilization in high power applications of multilevel inverters. As the primary effort for optimization of the SHE and SHM, a new switching angles has been obtained for a low switching frequency voltage waveform through the precise mathematic analysis on the triplen harmonics to self-eliminate all triplen harmonics without doing any extra calculations. Then, the determined non-triplen harmonics are eliminated or mitigated by the normal operation of the SHE or SHM. Therefore, maximum harmonics amplitudes are controlled while the switching frequency is at minimum. In the next work, SHE is optimally designed for 3phase 4wire inverters as to supply both symmetrical and asymmetrical loads under low switching frequency operation. SHE has been adaptably designed for both 4wire configurations of 3phase NPC inverter; 4leg 4wire and 3leg 4wire. It has been shown that SHE is more compatible with 3leg 4wire configuration over 4leg 4wire one in terms of harmonic distortion of output phase voltage, switching angles calculations and design complexity as well as power losses. Next work presents a hybrid strategy of SHM modulation technique for controlling CMV in 3phase inverters. In all previous works where software solution based on the modulation techniques was used to control CMV, the applied technique was deigned based on the proper selection of the switching vector. However, it the proposed work in this thesis, the CMV is controlled based on the harmonic analysis in order to formulize CMV in the hybrid SHM technique. It was shown that CMV is notably reduced by elimination of triplen harmonics while the switching frequency ratio is kept under 1KHz. Finally, last work introduces a novel compact multilevel inverter so-called as Packed E-Cell topology. Packed E-Cell is a deep optimization of previous generation of compact multilevel inverter; Packed U-Cell to reach further output voltage levels, reduced components counts and simplicity in capacitor voltage balancing. Packed E- Cell has been established based on the idea of extending the capacitors in horizontal way unlike vertical way which results in more optimized structure compared to Packed U-Cell. It was shown that the Packed E-Cell can be a suitable and reliable alternative topology to replace Packed U-Cell. All works are fully supported by theoretical, simulation and experimental analyses and discussion.

Date	21 Apr 2021
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Kamal Al-Haddad (Supervisor)