Self-timed processors use local synchronization mechanisms in the absence of a global clock signal. This specificity makes them less energy-consuming compared to synchronous processors. However, self-timed processors are less popular due to lack of design and verification tools as well as the rapid evolution of synchronous processors in terms of performance.
This thesis is part of the AnARM project which aims to develop a general purpose ARM processor based on a self-timed architecture. This thesis’s particular goal is the exploration of instruction scheduling methods in order to develop a scheduling strategy, based on the architectural features of the AnARM processor, with the aim of improving its performance.
Instruction scheduling is a compiler optimization that has a significant impact on the quality of the generated code. This optimization consists in solving an NP-complete problem while taking into account several constraints, imposed by the target processor’s architecture. While instruction scheduling for synchronous architectures benefits from a wide literature coverage, scheduling for asynchronous architectures has been less addressed, due to the new constraints imposed by the synchronization mechanisms used by these architectures.
This paper presents the development, implementation and evaluation of a scheduling strategy for the AnARM processor. The scheduling method presented in this thesis uses a dynamic scheduling model based on the spatio temporal behaviour of the AnARM. This method has been implemented within a modern commercial compiler and evaluated comparatively to usual scheduling methods. The scheduling method presented in this thesis yields performance improvements ranging between 6,22% and 17,48% while preserving the energy asset of the self-timed architecture under study.
| Date | 11 Apr 2017 |
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| Original language | French |
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| Awarding Institution | - École de technologie supérieure
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| Supervisor | François Gagnon (Supervisor) & Claude Thibeault (Co-supervisor) |
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Halli, H. (Author),
Gagnon (Supervisor) &
Thibeault (Co-supervisor),
11 Apr 2017Student thesis: Master's thesis › Master in Engineering: Engineering