Signatures des circuits ASIC - approche pour détermination des pannes systématiques

Abstract

This thesis explores different strategies for the detection of systematic defects in VLSI circuits based on the concept of signatures constructed from faults detected by the scan cells under test. Assuming that the nodes of a circuit and the area they occupy are related to the occurrence of faults in a chip, we can calculate the probability of a systematic failure and the signature of specific defects of this chip. By creating different signatures through the use of different information, the project examines the contribution of additional information, the signature related to the nodes surfaces being the most elaborate. In total, four types of signatures have been investigated. This typical DFM (Design for Manufacturability) approach involves fabrication parameters, like the parasitic capacitance or the metal layers as well as design parameters such as design rules margins for layout. It was required to develop various utilities and scripts complementing the commercial tools traditionally used in VLSI design. A comparative analysis of the results to determine the cause of systematic failures with different signatures is presented. Compared with the signature of constant weighting (assuming equiprobable faults), the signatures weighted by parasitic capacitances or the metal layers only provide little more details. For the last type of signature, weighted by the effective surface of DRC polygons, presented in three variants the extra work is larger. The three variants, obtained by handling Fastscan results differently, target more precisely the likely causes of systematic failures offering as a bonus, help in debugging the circuit, for the second and third alternative.

Date	7 Jun 2011
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)