Synthétiseur de fréquence pour les applications avioniques SDR: analyse et conception

Abstract

Nowadays, frequency synthesizers are widely used as local oscillators in modern front-end transceivers. They are used to generate required carrier frequencies for up and down frequency conversion. This dissertation will focus on the design and the analysis of a new frequency synthesizer architecture based on PLL able to cover a large spectrum and mainly the one used for avionic communications. The proposed frequency synthesizer provides a continuous frequency band reaching 10 GHz. This wide frequency range allows for enough agility in order to meet frequency specifications of several systems, while providing high accuracy and respecting phase noise, cost and power consumption constraints. Based on a comparative analysis of synthesizer architectures presented in the literature, simulations allow to choose the suitable architecture for the intended application. Subsequently, a general analysis performed on the PLL allowed distinguishing the design considerations as well as selecting of different characteristics and key parameters in order to meet the design requirements for each internal synthesizer block. A suitable VCO for the application has been designed depending on implementation considerations. Meanwhile, the phase frequency detector, the charge pump, the single side band mixer, frequency dividers and multiplexers are also designed while respecting frequency constraints and implementation considerations. Fully integrated in 0.13 μm CMOS technology, the frequency synthesizer provides a carrier frequency range from 100 MHz to 10 GHz covering numerous avionics communication applications and existing wireless communication standards. The VCO used provides a wide tuning range of 6.6 GHz to 10 GHz (40%). The VCO phase noise, measured at 8.3 GHz, is about -107 dBc/Hz at a frequency offset of 1 MHz with a power consumption of 3.4 mW. Thus, the VCO figure of merit (FOMV ) is 205. In addition, the synthesizer exhibits a total phase noise of -106.4 dBc/Hz at a 1 MHz frequency offset for a 8 GHz output frequency. The PLL loop bandwidth is of 110 kHz while the measured integrated jitter is about 637 fs with a measured PLL consumption of 15.7 mW which lead to a jitter FOMj of -232.

Date	21 Dec 2020
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Wessam Ajib (Supervisor) & Frédéric Nabki (Co-supervisor)