Hybrid Predistortion of RF Power Amplifiers with Nearly 25% Reduction in Digital Predistortion Complexity

This paper presents a hybrid analog-digital predistortion (HADPD) architecture combining an analog predistorter with a digital predistortion platform. The analog predistorter is designed to provide coarse linearization of the power amplifier (PA), thereby reducing the burden on the digital predistortion (DPD) stage. Measurements were carried out at 3.5 GHz, at 5 dB backoff from the 1 dB compression point at different signal bandwidths. Without predistortion, the PA exhibits an ACPR of -35 dBc, which improves to -42 dBc using the analog predistorter alone. When applying conventional digital predistortion with a 190-coefficient generalized memory polynomial (GMP) model, an ACPR of -54 dBc is achieved. By contrast, the proposed hybrid predistortion approach achieves an ACPR of -56 dBc using only 95 digital coefficients, a 50% reduction in the number of digital coefficients. This yields approximately a 25% overall reduction in DPD complexity and relaxes the requirement of the DPD's hardware. These results demonstrate that the analog predistorter effectively mitigates the dominant nonlinearities, enabling a substantially simpler digital predistorter to achieve superior linearization performance.