Impact of Clock Gating on IC Delay Testing: Experimental Results

This paper presents experimental delay measurements induced by clock gating, emulating both mission and test modes of integrated circuits. The experiments were conducted on various commercial FPGA-based boards. The results indicate significant delay variations caused by clock gating. Notably, the delay variation between different board models exceeds that observed among multiple copies of the same model. Furthermore, the transient phases induced by clock gating exhibit distinct patterns across board models, influencing the timing of worst-case scenarios in both mission and test modes. The impacts on IC delay testing, mainly test escapes and yield losses, are analyzed and discussed.