PMC-assisted runtime workload-aware power-state adaptation using OS-level actuation

Modern processors support dynamic power management, but default Operating System (OS) policies often rely on broad, high-level CPU usage and may miss microarchitectural workload behavior. Simulator-based studies have shown that PMC-derived workload signals can guide energy-efficient scheduling and power adaptation, but their effectiveness on real hardware remains uncertain because practical platforms introduce measurement noise, OS interference, monitoring overhead, delayed power-state response, and limited actuation interfaces. This paper addresses this gap with a user-space Performance Monitoring Counter (PMC)-guided Dynamic Power Management (DPM) technique, implemented and evaluated on real hardware through Windows-based OS-level power-plan actuation. The controller samples PMCs and CPU utilization using Intel PCM and switches native Windows power plans through powercfg. Two schemes are developed: FT-PMS maps instantaneous PMC values to OS-level Low, Medium, and High states, implemented as the Windows Power saver, Balanced, and High performance plans rather than direct voltage-frequency settings. SW-PMS adds sliding-window averaging, majority voting, and hysteresis to stabilize FT-PMS decisions. Across CPU-intensive, memory-intensive, and mixed workloads, SW-PMS reduces total CPU energy by 5.3%, 6.8%, and 7.5%, respectively, relative to the Windows default Balanced state. IPC, measured effective frequency, CPU utilization, and power-state residency results show that these savings are achieved while maintaining comparable or higher processor-activity and instruction-progress indicators in the representative workload classes.