Étude de l’effet du conditionnement de l’horloge sur les modes test et mission dans les circuits FPGA

Abstract

This master’s project focuses on evaluating the representativity of the test mode compared to the mission mode in the presence of Clock Gating, a clock conditioning technique widely used to reduce power consumption in electronic circuits. However, this technique generates Power Supply Noise (PSN), causing transient voltage fluctuations in the Power Delivery Network (PDN), which disrupts signal propagation delays. An optimized delay line architecture was developed to assess delay variations over a wide frequency range. The Launch on Capture (LC) delay fault testing technique was applied in test mode. A Pause parameter was also introduced to precisely control the timing of LC application. Additionally, different flip-flop switching activity ratios were tested to evaluate their impact on delays. Two FPGA platforms, ZC702 and ZEDBOARD, were used on to analyze their transient behavior in response to PDN impedance variations in terms of delays. An optimization algorithm was adapted to explore different combinations of LC and Pause parameters, enabling the identification of the most representative configuration. Experiments in mission mode confirmed the presence of two transient phases : the first occurs at the injection of noise, while the second begins when the noise is stopped. However, in test mode, the noise remains active during both transient phases. The results reveal that ZEDBOARD exhibits better representativity when configuring a single Launch transition followed by a Capture transition. Likewise, the number of flip-flops in a noise generator block is directly proportional to delay values. Finally, for both FPGA models, the test mode systematically underestimates delays, highlighting the impact of PDN impedance variations on measurement accuracy.

Date	22 May 2025
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)