Amélioration de la technique de test et diagnostic CDIDDQ

Abstract

This thesis aims to improve the CDIDDQ test and diagnostic technique. The experiments consist in improving the CDIDDQ application, previously developed by Haithem, to detect short-circuit type defect in a FPGA circuit. This thesis begins with an introduction to basic concepts as well as a literature review describing integrated circuit fault concepts, FPGA fault emulation, current-based test techniques, and previous work on the CDIDDQ test technique applications. Subsequently, the CDIDDQ test pattern generation technique as well as its associated vectors is presented. Simulation was used to validate test patterns in order to apply them on FPGA integrated circuits. We redid Haithem’s (2011) experiment using a different measurement system, which produced almost identical results. Afterwards, modifications were done on the setup in order to reduce power induced noise as much as possible. The same FPGA was used but on a different prototype board, which increased the ability to detect short circuit defects. We also looked into the application of the technique on energy-hungry circuits from 70mA to 3A. Finally, the applied experimentation techniques with which we obtained the best results is laid out in detail. At that point, a different setup was used, as well as a different architecture for the CDIDDQ tester, a different acquisition technique and a software custom made for CDIDDQ tests. These modifications allowed us to detect bridge faults with a current five times smaller.

Date	10 Jan 2014
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor) & Ghyslain Gagnon (Co-supervisor)