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Amélioration des méthodes d’émulation des pannes par les radiations cosmiques sur les FPGA

Translated title of the thesis: Improvement of fault injection methods under the effects of cosmic radiations
  • Mariem Laouej

Student thesis: Master's thesisMaster in Engineering: Electrical Engineering

Abstract

The earth is bombarded by a stream of energetic charged particles called cosmic rays. The effects of cosmic rays on microelectronics are known and are of increasing concern, especially for on-board systems in airplanes flying at ever-higher altitudes. Indeed, the decrease in the size of transistors has resulted in circuits that are generally more sensitive to cosmic radiation. In this context, it is important to investigate the reaction of these embedded systems to radiation. If accelerated tests under particle beams remain the most realistic way to do this investigation, other techniques, such as emulation, allow to initiate this task. The objective of this project is the enhancement of a method of fault injection by emulation in terms of representativeness as well as in terms of speed for the most faithful reproduction of the results of the tests under neutron beams obtained at the TRIUMF laboratory in Vancouver. In this thesis, a series of fault injection experiments are performed while targeting specific parts of the configuration memory of the circuits used. The circuits used in our experiments are SRAM-based FPGAs, which are a popular choice in aerospace environments. The type of targeted failures, very frequently encountered in SRAM memory components, is the SEU (single event upset), which is the usual effect of a neutron passing through a sensitive region of a microcircuit. We propose a new method, which consists in attacking the essential parts of the LUT (Look Up Table) bits, representing the smallest configurable entity of the FPGA allowing the implementation of simple logic functions, as well as the Non-LUT bits, representing the other configuration bits, while considering the difference in sensitivity between these bits. This approach is efficient, it contributes to the achievement of our objective, and it allows an estimation of the number of critical bits.
Date29 Jul 2021
Original languageFrench
Awarding Institution
  • École de technologie supérieure
SupervisorClaude Thibeault (Supervisor)

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