Analysis of clock gating impact on FPGA behavior

Abstract

This master's project is concentrated on finding the noise effect on delays and defining the worst-case scenario in the functional mode while clock gating is applied to the measurement circuit. In the literature review, efforts are made to verify that clock gating is one of the most practical power consumption reduction technique in FPGA-based design. However, the point that is considered in the measurement is that clock gating could induce noise on VDD with other parts of the design that remain active. To avoid unwanted fluctuations such as intermodulation due to the use of multiple clocks, only one clock is used. The proposed design includes two different delay lines. Both delay lines are used to calculate the noise effect in the design with this difference, one creates a thermometer coded output, and the other creates both thermometer coded output and pulses. The pulses are representative of different delays in the design. The results confirm the presence of two transient phases: one when the noise is started and the other one when the noise is stopped. Fluctuations in delay appear in both phases. Starting the noise overall slows down the combination logic while stopping the noise makes it faster.

Date	13 Aug 2021
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)