Automated SEU fault injection framework using the Xilinx SEM IP on Zynq UltraScale+

Abstract

Field Programmable Gate Arrays (FPGAs) are widely deployed in safety-critical and radiation exposed environments, including aerospace, high-energy physics, and edge AI systems. In SRAM-based FPGAs, the configuration memory is vulnerable to Single Event Upsets (SEUs), which are bit flip events caused by ionising high-energy particle strikes. An SEU in configuration memory can silently alter the logic of an implemented circuit and remain until the device is reconfigured, making reliability assessment of FPGA designs a core engineering concern. AMD1’s Soft Error Mitigation (SEM) IP core provides a built-in solution for emulating SEUs by controlled bit injection into the configuration memory of FPGAs to investigate the reliability of FPGA designs. Despite the capabilities of this IP core, comprehensive fault injection campaigns using the SEM IP have required significant manual effort, limiting the scope and reproducibility of reliability studies. This thesis presents an automated Python-based framework that drives the SEM IP over a UART interface to conduct systematic fault injection campaigns on the FPGA platform with minimum manual intervention. The framework automates the full injection cycle: initiating an injection, monitoring the design-under-test (DUT) response via UART, logging outcomes, and resetting the SEM IP for the next injection. Three case studies demonstrate the framework’s applicability across different design types. The first is a finite state machine (FSM) proof-of-concept implemented as three parallel instances driven by a configurable Linear Feedback Shift Register (cLFSR). The second and third are fault injection campaigns on two RISC-V32I soft-processor cores running a Fibonacci sequence generator and a fixed-point binary image classifier, respectively. The results quantify the critical bit fraction of each design and characterize the failure behaviours produced by SEUs, including silent data corruption, computation errors, and system stalls. The framework is designed to be design agnostic, requiring only a UART communication channel, and is extensible to any SEM IP compatible target. This work addresses a gap in automated reliability assessment using AMD SEM IP and provides a reproducible methodology for pre-deployment SEU characterization of FPGA-based designs.

Date	25 Aug 2026
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor) & Mostafa Darvishi (Co-supervisor)