Comparaison des stratégies de synchronisation pour circuits intégrés

Abstract

This thesis focuses on comparing four synchronization strategies found in integrated circuits to evaluate their performance after implementation with computer-aided design tools used in the industry. It includes three strategies recognized in the scientific community : the synchronous strategy, the asynchronous bundled-data strategy, and the wave pipelining strategy, as well as a new strategy proposed by Michel Kafrouni, the pseudo-asynchronous strategy with clock borrowing. Moore’s Law, which states that the number of transistors in an integrated circuit doubles every two years, has led to the widespread use of the synchronous synchronization strategy in the semiconductor industry. However, in recent years, there has been a significant slowdown in the development of manufacturing processes, limiting the performance improvements of systems using this strategy. To date, several synchronization strategies offer improvements over the synchronous strategy. First, there is the asynchronous bundled-data strategy, which uses controllers to self-regulate the circuit’s timing. Next is the wave pipelining strategy, which pushes performance limits by modelling combinational delays as a transmission line. Finally, there is the pseudo-asynchronous strategy with clock borrowing, which proposes a hybrid between the synchronous and asynchronous strategies to exploit their advantages. Due to the design incompatibility of non-synchronous strategies with computer-aided design tools, unconventional methods had to be used to constrain static timing analysis. First, the local clock set method was used to model the asynchronous strategy. Next, a new method was designed to model wave pipelining based on equations found in the scientific literature. Finally, a new method was also designed in collaboration with Michel Kafrouni to implement the pseudo-asynchronous strategy with clock borrowing. The results obtained in this research highlighted the potential offered by the pseudo-asynchronous strategy with clock borrowing. At equal performance to the other strategies, it demonstrated a reduction in the area used as well as a reduction in power consumption for large circuits. Improvements to the method developed for this strategy are recommended to optimize power consumption associated with the clock network without human intervention.

Date	19 Sept 2024
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)