Conception d'un SAR-ADC de 10/13-bit à 83kS·s-1 avec fonction de dithering

Abstract

The main goal of this projet is to study the implementation possibilities of a variable resolution technique for SAR-ADC (successive approximation register - analog to digital converter). This system uses a dithering technique to increase the native resolution from 10 bits to 13 bits. In order to evaluate the performances of such a system, a circuit has been designed in Global-Foundries CMOS 130nm technology. This report describes the design, simulation, fabrication and test of such a converter. Computer simulations revealed interesting preformances in native mode with a medium ENOB of 9.88 bits. In simulation, the resolution reaches 11.4 bits with the dithering technique. Unfortunately, problems in the fabricated chips have prevented the experimental validation of this concept. The last section of this report is based on theoritical considerations and offers the improvement of performance by replacing the averaging dithering by a binary search algorithm. In this case, such a modification would reduce the number of conversions from 15 to 4 to have the same result. A paper called "A Calibration-Free 13-Bit 0.9 V Differential SAR-ADC with Hybrid DAC and Dithering" has been accepted at the 2017 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Date	8 Jun 2017
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Nicolas Constantin (Supervisor) & Frédéric Nabki (Co-supervisor)