Mise en oeuvre et validation d’une méthodologie estimant la sensibilité des blocs d’entrée/sortie des FPGA à base de SRAM face aux radiations

Abstract

Nowadays, the effects of cosmic rays on electronics have become the pre-eminent concern of researchers who are interested in the robustness of integrated circuits. Many researches have been elaborated in this direction, mainly for aerospace applications where the environments are dense in terms of particles which can lead to the dysfunction or even to the destruction of these applications, when interacting with integrated circuits. Radiation tolerant circuits seem to be a good solution to improve the robustness of these circuits. However, those circuits are generally more expensive and their technologies often lag a few generations behind nontolerant circuits. Designers prefer to use conventional circuits and apply mitigation techniques to improve the tolerance of soft errors. To improve the tolerance and the reliability of conventional circuit, it is necessary to analyze the vulnerability of these circuits in different levels of abstraction in the design flow. Conventional design methodologies need to be adapted in order to evaluate the tolerance to errors caused by radiation. In this Thesis, we are mainly interested to elaborate and validate a methodology allowing the estimation of the sensibility of resources required to implement avionics applications in SRAM-based FPGA, against single events (SEU) and multiple events (MBU). In fact, the SRAM-based FPGA are increasingly used by the aerospace community due to their rapid prototyping and on-site reconfiguration characteristics, although they are vulnerable to radiation. We propose a new methodology to study the effects of single events (SEU and MBU) on the input/output blocs (IOB) of SRAM-based FPGA. More precisely, this study propose a delay model to characterize the impacts of these events on IOBs. In the same context, this Thesis is based on the study of two Xilinx FPGAs (Virtex-5 and Artix-7). Two different techniques were used to generate SEUs, namely fault injection and irradiation experiments. The results from irradiation showed the existence of delays in the IOBs up to 6.2 ns for the Virtex-5 and up to 3.8 ns for the Artix-7. Those results were validated by fault injection using the SEU Controller. This thesis also presents a further study of the effect of radiations on the delays observed in the IOBs of SRAM-based FPGAs. More precisely, this research propose and validate delay models allowing to describe and better understand the mechanisms that can lead to the delays observed in IOBs. A final aspect of this thesis is the study of the reliability and the robustness of some mitigation techniques applied inside the IOBs of SRAM-based FPGAs. Important observations have revealed that the SEUs affecting the IOBs can make the correction and reconfiguration techniques (Scrubbing) insufficient to correct and avoid the accumulation of several errors. These observations led to a reflection on the type of adequate mitigation technique that must be used in IOBs in the presence of SEUs.

Date	28 Aug 2017
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor) & Yvon Savaria (Co-supervisor)