New circuits for time-domain signal processing in low-voltage CMOS

Abstract

Aggressive scaling of CMOS technology in sub-100 nm process motivates the replacement of voltage or current-mode signal processing with time-mode approaches which uses digital circuits to perform signal processing. As the time difference between two signals is independent of the amplitude of either signal, intuitively, a time-mode (TM) signal representation is believed to be more compatible with newer CMOS processes that operate at lower power supply levels. It is the objective of TM circuit architects and researchers to identify new circuit architectures that can perform basic signal processing operations such as adding, subtracting, multiplications, etc. At the heart of these efforts is the need to identify TM circuits that perform such operation at high performance levels; levels that equal or exceed those of voltage-mode (VM) circuits at similar power levels. In the first phase of this thesis, an intensive review of the literature is presented. The review includes ΔΣ analog-to-digital converter (ADC) specifications and all the major developments in the area of TMΔΣ converters in the last decade. Then we present a rigorous comparison between discrete-time TM circuits and continuous-time VM circuits to identify gaps that need to be filled. As a first contribution, we provide an analytical expression for the noise operation of both a VM and TM PMOS-NMOS transistor stack, leading to the expression of the peak-SNR of both architectures. The proposed noise theory is applied to different CMOS process and compared in Spectre. In addition, we provide IC implementations with measurement results to verify the analysis finding. Then, as a second contribution, we propose new TM building blocks and extensions to some old ones that alleviate the challenges imposed by modern CMOS technologies, without affecting the performance metrics. The first challenge is the need for half-period delay and full-period delay unit for TM circuits; the second challenge is the need for TM circuits to perform basic arithmetic operations (i.e., addition or subtraction) in wide linear range; and the third challenge is how to realize negative feedback in time-domain and process signals at higher frequency around intermediate frequency (IF). As a third contribution, an all-digital realization of a TM lossless discrete integrator (LDI)- based resonator is presented. The resonator is constructed by new TM building blocks in a negative feedback configuration. This achieves high-speed time-mode signal processing without the limitations imposed by switched-capacitor (SC) circuit techniques such as the matching of capacitors to realize precise signal gains. Instead, circuit precision is realized using an adaptive delay circuit to adjust the loop delay in a wide range of sampling frequencies. The operation of the TM LDI-based resonator is validated with transistor-level simulations and compared with system-level in Simulink/MATLAB. Finally, we propose a novel highly-digital BPΔ ΣTDC for IF applications. It first introduces the system architecture of the proposed design and presents the expected performance metrics. The BPΔΣTDC is able to shape the quantization noise in a negative feedback configuration, and it does not require any complex calibration circuit to compensate for timing errors. In addition, for the very first time in TMSP, a direct feed-forward compensation is utilized in the TDC to achieve high signal-to-noise and distortion ratio (SNDR). We demonstrate the proposed TDC in an IBM 130 nm CMOS process, while operating from a supply voltage as low as 1.2 V. A continuous sampling frequency range from 4 MHz to 42.8 MHz is achieved to digitize an input signal that is centered at one-quarter of sampling frequency. It achieves a 39.5 dB peak SNDR over a 0.2 MHz signal bandwidth at maximum sampling frequency fs =42.8 MS/s while consuming lower than 5 mW power. Furthermore, we identify future directions in TM circuit design and high-order realization of BPΔ ΣTDC for research.

Date	1 Nov 2018
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Ghyslain Gagnon (Supervisor) & Gordon W. Roberts (Co-supervisor)