Nouvelle technique de test de type délai plus robuste à la variation d'impédance du réseau de distribution d'alimentation

Abstract

Nowadays, Scan Based at-Speed Testing (SBAST) is the most dominant delay testing approach. This type of test comes with some drawbacks, such as power supply noise (PSN) produced during the test mode, which differs from that induced during the functional mode. Some SBAST techniques have been proposed to reduce PSN. However, one particular aspect has been overlooked in the literature, namely the impact of Power Distribution Network (PDN) impedance variation on delay testing. This thesis presents a new SBAST test technique, called One Clock Alternated Shift (OCAS), to minimize the potential impact of the PDN impedance variation. The strategy behind this new technique is to mimic as much as possible the clock signal of the functional mode. The purpose behind this strategy is to obtain power distribution conditions similar to those of the functional mode in order to protect the circuit under test mode against power variations due to impedance variation. As a case study, we consider the PDN impedance variation that can occur with 3D integrated circuits, more specifically when a top die under test is bounded over a stack of different sizes. HSPICE simulation results show that the OCAS is less sensitive to such impedance variation and outperformed from an overall perspective the main existing SBAST techniques. Moreover, results obtained with ATPG tools (Automatic Test Pattern Generation) show that OCAS fault coverage is very acceptable for all simulated cases. However, it comes at the expense of additional test patterns, due to the ATPG tool limitations.

Date	8 Aug 2017
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor)