Optimization of very low time step FPGA-based simulations using a fixed admittance matrix approach

Abstract

This research is dedicated to the study of the fixed admittance matrix approach presented by Pejovic and Maksimovic (1994). More specifically, this work has three objectives. First, to study and quantify the effects of this method on simulation accuracy. Second, to use this knowledge to develop a method to tune the Gs parameter without relying on a trial and error process. An algorithm is proposed to automatically optimize the Gs parameter which has been validated on three topologies: a two level inverter, a three level NPC inverter, and a direct matrix converter. Third, to explore possible solutions that conserve the advantages of a fixed admittance matrix approach (small time step, low memory consumption) while mitigating its drawbacks (loss of simulation accuracy). A method is proposed which offers the accuracy of a variable admittance matrix approach, but with significantly less memory consumption. This method has been validated offline, however, it remains to be seen if it is a viable candidate for real time implementation and more research must be done.

Date	19 Dec 2014
Original language	American English
Awarding Institution	École de technologie supérieure
Supervisor	Handy Fortin Blanchette (Supervisor)