Prédiction et analyse statistique des performances des circuits asynchrones dans un contexte d’adaptation dynamique de la tension d’alimentation

Abstract

The analysis of asynchronous circuits is of crucial importance in the design and optimization of electronic systems, ensuring reliable and efficient performance. This thesis delves into two crucial aspects of asynchronous circuit analysis. In the first part, the thesis explores delay constraints for Single-Rail Bundled-Data Handshake- Free (SRBDHF) circuits using Dynamic Voltage Scaling (DVS) to manage power consumption. An innovative model is proposed to define these constraints, covering various aspects such as synchronization, degradation of the synchronization signal, and the sensitivity of logic gates to changes in supply voltage. These constraints, not explicitly formulated before, are crucial to ensure temporal compliance. Simulation results highlight the feasibility of meeting these constraints with DVS, but also suggest that adjustments may be necessary to optimize signal propagation and operation efficiency. The second part of this thesis introduces a statistical performance analysis model specifically tailored to asynchronous pipelines. This model is applicable to two styles of asynchronous circuits, SRBDHF and Click Element (CE), and enables effective performance evaluation in the face of variations in manufacturing process, voltage, and temperature. It includes a delay variability model to assess the impact of manufacturing process variations on performance, as well as a statistical performance analysis model incorporating various logical and temporal constraint checks. Accounting for supply voltage variation in the analysis, from the nominal region to the near-threshold region, as well as temperature variations, is essential for verifying different statistical constraints. Results demonstrate that this model offers reasonable accuracy, with an average error of only 2% compared to detailed analyses based on low-level Monte Carlo simulations. Moreover, this method allows for a rapid assessment of asynchronous circuit performance, significantly reducing the time required for in-depth analyses. These two aspects of the thesis make a significant contribution to asynchronous circuit analysis, providing promising insights for the advancement of the design of these circuits

Date	10 Oct 2024
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor) & Yvon Savaria (Co-supervisor)