Stratégies facilitant les tests en pré-certification pour la robustesse à l'égard des radiations

Abstract

Over the last few decades, researchers have been interested by the robustness of integrated circuits and the effects of cosmic radiation on embedded electronics. Many researches have been elaborated in this direction, mainly for the aerospace applications where their deployment’s environments are hostile. In fact, these environments are dense in terms of particles which, when interacting with integrated circuits, can lead to their dysfunction or even to their destruction. In addition, radiation effects are amplified for the new générations of integrated circuits where the shrinking size of transistors and the circuits’ complexity increase augment the occurrence probability of anomalies and consequently increase the test need. The expansion of commercial-off-the-shelf (COTS) electronics and the adoption of these components for critical applications such as aerospace applications is another indicator inciting to double the efforts of circuits’ robustness verification. Despite their better characteristics in comparison with their rad-hard counterparts, which are expansive and built with technologies few nodes down, COTS are vulnerable to radiations. In order to enhance the robustness of these circuits, an evaluation of their vulnerability in different levels of abstraction in the design flow is recommended. This helps the designers to take the necessary mitigation measures for the design in the appropriate abstraction level. Finally, to satisfy the requirements of building robust circuits, costly certification tests using particle (e.g. protons, neutrons) beam have to be performed. In this thesis, we are mainly interested in defining a pre-certification strategy allowing to realistically evaluate the sensitivity of integrated circuits towards radiation in order to avoid sending non-robust circuits to the costly phase of certification. SRAM-based FPGA are the circuits targeted by our work and SEUs (single event upsets), consisting of a switching of a logic state of a memory element to its complementary, caused by radiation are the targeted faults. In fact, SRAM-based FPGA are more and more in demand by the Aerospace community due to their characteristics of rapid prototyping and on-site reconfiguration, but they are vulnerable to radiations where SEUs are the most frequent faults in memory elements of SRAM. We propose a new fault injection approach by emulation allowing to mimic the radiation effects on the FPGA configuration memory and to generate results as faithful as possible to those of certification tests. This approach is based on considering the sensitivity difference between configuration bits set to '1' and those set to '0', observed by tests under proton beam at the renowned TRIUMF lab, in the procedure of test sequences’ generation in order to mimic the faults distribution in the configuration memory. The results of validation experiments show that the proposed strategy is efficient and generate realistic results. The same results reveal that non taking into account the sensitivity difference may lead to the underestimation of the circuit sensitivity. In the same context of optimizing the procedure of fault injection by emulation, i.e. the precertification test, we propose a methodology maximizing the detection of critical bits (bits causing functional failure if they change state) for a given number of SEU (which is the adopted fault model) or maximizing the precision of critical bit number estimation. To do so, a classification of configuration bits in different sets according to their contents, the resources that they configure and their criticality, is first done. Then, an evaluation of the sensitivity of each set is accomplished. Finally, prioritizing fault injection in the most sensitive sets is recommended. Many scenarios of fault injection optimization are proposed and the results are compared with those given by the conventional random fault injection. The proposed optimization methodology ensures an improvement of more than two orders of magnitude. Another approach facilitating the evaluation of the FPGA utilized LUTs (look up tables) configuration bit sensitivity is presented, where LUT are the smallest FPGA configurable entities allowing to implement combinatorial functions. It allows easily identifying the LUT configuration bits at no cost in terms of hardware or external tools utilization. The proposed approach is simple and efficient, offering a 100 % fault coverage, and applicable to new Xilinx FPGA generations. The proposed approaches contribute to meet the requirements of the specifications of this thesis and complete the goals set. The realism and the maximization of the estimation of circuits under test vulnerability offered by the new approaches ensure the elaboration of an efficient pre-certification strategy. In fact, the first fault-injection approach considering the relative sensitivity difference of memory elements according to their content generate results giving a relative error attaining 3.1 % when compared to results obtained at TRIUMF, whereas relative error given by the comparison of the results of a conventional random fault injection with those obtained at TRIUMF can reach a value of 75 %. In addition, the application of this approach to more conventional circuits shows that 2.3 times more errors are detected in comparison with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation procedure can lead to an underestimation of a design sensitivity to radiation. The results of the second proposed approach were also compared to random fault injection results. The proposed approach, maximizing the number of flipped critical bits, allows speedup factors up to 108 of fault injection procedure in comparison with the random approach. It also allows minimizing the number of critical bits estimation error to attain a value of ±1.1 % calculated for a 95 % confidence interval, whereas the value of critical bits estimation error generated by therandom fault injection approach for the same confidence interval can reach ±8.6 %. Finally, the last proposed approach of fault injection in the LUTs can be distinguished from the other approaches in literature by its simplicity while ensuring maximum fault coverage of 100 %. In fact, the proposed approach is independent from external tools permitting to identify the bits configuring the LUTs which are usually obsolete or do not support the new générations of FPGAs. It acts directly on the files generated by the adopted synthesis tool.

Date	30 Nov 2016
Original language	French
Awarding Institution	École de technologie supérieure
Supervisor	Claude Thibeault (Supervisor), Yves Blaquière (Co-supervisor) & Raoul Velazco (Co-supervisor)